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Testbench til SystemVerilog

SpringsSoft lancerer en omfattende SystemVerilog Testbench (SVTB) løsning (in english).

SpringSoft, Inc., a global supplier of specialized IC design software, today announced comprehensive SystemVerilog Testbench (SVTB) debug support with the latest release of its Verdi Automated Debug System. 

The Verdi system introduces a new structured message-based method for automating SVTB debug so engineers can quickly comprehend complex testbench behavior. The Verdi SVTB debug solution is fully integrated with SpringSoft’s family of Novas Verification Enhancement products that let engineers do more verification in less time.


The new release of the Verdi system integrates an automated message-based logging mechanism and new testbench-specific comprehension tools for SVTB that works with the Verdi system’s existing HDL debug capabilities. 

The system also provides an interactive simulation mode that can be used to pinpoint issues that are not revealed through logging. These unique capabilities are delivered within the system’s unified testbench and design debug environment to enable more efficient recording and post-processing of dynamic testbench data and save valuable verification cycles by reducing the need for interactive debug.  

- SVTB provides a higher-level, software-like approach to verification, says Oz Levia, VP of Product Marketing at SpringSoft.
- Verdi offers a unique structured approach to automating SVTB debug that deals with the abstract and dynamic nature of testbench verification.  With insight into complex testbench behavior that is correlated to activity on the design side, engineers can observe what is going on in the entire design and verification environment.

Advanced SVTB Debug

The Verdi system provides full SVTB source code support with tight synchronization between the data coming from the design and the testbench.  The Verdi system automatically records testbench messages and data into SpringSoft’s defacto standard Fast Signal Database (FSDB).

This provides a high-level view of testbench activity that can be analyzed alongside design data (value changes and assertion states) also contained in the FSDB to give a complete picture of the behavior of the entire environment. 

New easy-to-use class and function browsers support the declarative nature of testbench-specific coding styles. These specialized Testbench Browsers enable engineers to visualize SVTB structures and simulation results, easily navigate the hierarchy of testbench modules, and automatically trace through source code to understand complex testbench code and to identify the origin of testbench problems.

In addition, the Verdi system seamlessly integrates the automated logging mechanism with an interactive simulation mode that works with popular third-party simulators. This enables engineers to perform a more detailed analysis of testbench behavior at specific locations and times.

SpringSoft has published a detailed technical paper describing this automated, structured method for SVTB testbench debug and analysis. It is available for download from the SpringSoft web site at: http://www.springsoft.com/technology/technical-papers/verification-technical-papers/SystemVerilog-Testbench-Debug-and-Analysis.

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