Send til en ven   Udskriv27/7 2009 kl. 14:44
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Første TLM-drevne design- og verifikations-løsning

Cadence booster produktiviteten med ny TLM dreven design- og verifikationsløsning (in english).

Cadence Design Systems has introduced the first unified TLM-driven design and verification solution and methodology enabling SoC designers to reap the benefits of transaction-level modelling (TLM).

The Cadence solution combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability, Incisive Enterprise Simulator with new TLM/RTL metric-driven verification and source level debug visualisation, Calypto sequential logic equivalence checking, the first version of the TLM-driven design and verification methodology, and customer adoption services.


The new solution enables SoC TLM IP to be designed, synthesised and verified, resulting in faster design creation, increased functional verification productivity, and more opportunities to reuse design and verification IP.

- We have been employing high-level synthesis and TLM verification for several years, and verification methodology has proven to be quite challenging, says Raimund Soenning, hardware development manager, Graphics Competence Center, Fujitsu Microelectronics GmbH.
- The Cadence methodology addresses the challenges we’ve experienced applying metric-driven verification from TLM through RTL, and mixing the two. We see significant opportunities to increase the reuse of our design and verification IP by following the comprehensive Cadence methodology.

The new TLM-driven design and verification methodology encompasses SystemC modelling guidelines for virtual platforms and high-level synthesis, and defines the process for performing multi-language OVM-based functional verification of TLM, TLM/RTL, and RTL. The methodology will be delivered in the form of manuals, self-paced tutorials, and workshops with hands-on labs.

New solution capabilities include migration from C/C++ to enable automatic conversion of legacy design sources to SystemC TLM; high-level synthesis integrated with popular memory compilers to optimise for each architecture; and side-by-side analysis and traceability of SystemC and synthesised RTL.

- Transaction-level design and verification is a reality, says Brian Bailey, of Brian Bailey Consulting.
- The individual pieces have been developed, and Cadence has accomplished the first steps in making them work together in a unified methodology.

The new TLM-driven methodology improves productivity, design quality, and project schedule predictability. Unlike prior technology, this comprehensive new solution enables customers to reuse TLM design and verification IP as golden source.

- Cadence is uniquely positioned to combine design and verification of TLM/RTL environments to address critical barriers to adoption, says Michael McNamara, vice president and general manager, systems software group, Cadence Design Systems. “Focusing on the complete needs of the customer, we are delivering on the full promise of system-level design productivity.

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