Send til en ven   Udskriv11/12 2009 kl. 9:44
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Cadence styrker designværktøjer

Cadence introducerer nu en række markante forbedringer til firmaets Virtuoso analog og mixed signal IC-designplatform (in english).

Cadence Design Systems now introduces dramatic improvements to its leading Virtuoso mixed-signal chip design platform.

The company announces powerful performance, capacity and usability enhancements in Virtuoso IC6.1.4 that reduce overall design time while ensuring high-quality production ICs. These enhancements will benefit design teams working along the full spectrum of design complexity, from the most advanced-node, cutting-edge designs to more traditional chips. 

The new Virtuoso release has been extended to work efficiently at advanced nodes down to 28 nanometers and now supports 64-bit processing for improved capacity and performance. The Virtuoso Space-Based Router has been integrated into the Virtuoso Layout Suite cockpit, making it easier to access.


More importantly, it now provides design teams a single common router they can use from start to finish to help ensure consistent results. Additional time-saving, quality-enhancing updates have been made to the Virtuoso Analog Design Environment XL, and Cadence design constraints technology.

Integrating the Virtuoso Space-Based Router into the Virtuoso Layout Suite brings the power of a 1 million net-capable router to the desk of every layout engineer.  Interactive wire editing and full chip automatic finish routing share the same algorithms, providing a seamless flow for a higher quality of design, from IP module creation though full chip sign-off.

Improvements to the Virtuoso Analog Design Environment XL include new display capabilities within the product that can now produce more, and better, datasheets. The Virtuoso Analog Design Environment’s ability to analyze multiple tests simultaneously, including those across corner and statistical variations, helps engineers pick the best circuit design directions early in the design cycle, and verify those choices efficiently post implementation. 

The Cadence design constraints methodology, which can help engineers reduce layout optimization and design refinement times by as much as 20 percent, received a boost in the new release, with enhancements that make it easier to add design constraints. In addition, there are new design constraints specifically geared to address sub-45-nanometer design yield challenges.

The new release extends the Cadence ExpressPcells capability to support multiple-user sites. Now customers can use their vast libraries of SKILL-parameterized cells anywhere and see up to an 8 times performance improvement. Cadence also improved the analog display technology to handle multi-gigabyte waveform files more efficiently. And Cadence removed the two-gigabyte limit on waveform databases to account for today’s larger, more complex designs. Finally, performance has been boosted for underlying design rule engines.

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