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Gennembrud for 3D IC teknologi

ST-Ericsson og forskningscentret CEA-Leti præsenterer et vigtigt gennembrud inden for tredimensionel IC-stacking og Wide I/O interfaces (in english).

CEA-Leti and ST-Ericsson will December 13 present a paper, that details the creation of a prototype of the world's first 3DIC with a three-die stack, an important milestone in validating and testing essential 3D technologies including Wide I/O memory and inter-chip communications protocols. The design is the result of a close collaboration among CEA-Leti, ST-Ericsson-a world leader in wireless platforms and semiconductors, and EDA-gigant Cadence Design Systems. 

The design integrates three stacked dies, integrating a Wide I/O DRAM memory stacked on top of two identical SOC logic die that incorporate multiple processor cores on each die.


TSVs (through-silicon vias) connect these three die together and in order to minimize the impact of the TSVs on signal integrity, the 3D stack employs an asynchronous Network on a Chip (NoC) for both die-to-die and intra-die communications.

The 3D-friendly NoC employs asynchronous serial links and achieves 550M transfers/sec throughput in the 2D (intra-die) direction, and 200M transfers/sec in the 3D (inter-die) direction.

Together with the high throughput and low power Wide I/O memory interface, this advanced three-die 3D prototype represents a first proof of concept, clearly demonstrating how these technologies can be employed to efficiently stack memory and logic for future 3D multi-processor architectures.

For its part of the joint project, ST-Ericsson developed WIOMING, the first application processor SOC integrated with a Wide I/O memory interface. Combined with Wide I/O technology, TSV and fine-pitch bumping technologies permit massive, high-bandwidth interconnect between the DRAM and SOC with very low capacitive and inductive loading. This approach also reduces interface power dissipation in the DRAM and logic die.

The ST-Ericsson WIOMING SOC provides 12.8GBytes/s of memory bandwidth - a 50 percent increase over the latest available dual channel LPDDR2 solutions at 533MHz at 20 percent less power. In addition, increasing the DRAM interface clock frequency to 266MHz and switching to DDR (dual data rate) mode will allow ST-Ericsson to create designs that deliver more than 34GBytes/s in future products, enabling unprecedented graphics and CPU performance in product such as smartphones and tablets.

Cadence has worked closely with ST-Ericsson and Leti to deliver the design tools and methodologies necessary for enabling this breakthrough three-layer 3D IC.
The company developed an automated and integrated 3D/TSV design solution employing the industry-leading physical implementation and analysis features in its Encounter Digital Implementation (EDI) System, Virtuoso Analog Design Environment, and QRC parasitic extraction tool. The project design team then used these tools to address complex timing, signal integrity, and thermal challenges in the 3D design.

As a result of this collaboration on tools and methodology, the design teams have successfully taped out multiple 3D/TSV designs. In addition, the teams incorporated the Cadence Wide I/O memory controller design IP into the design of the WIOMING SoC, ensuring exceptionally high bandwidth memory. 

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